Android_verify/third_party/android-libs/share/man/man3/OPENSSL_ia32cap.3ossl

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.\" ========================================================================
.\"
.IX Title "OPENSSL_IA32CAP 3ossl"
.TH OPENSSL_IA32CAP 3ossl "2024-09-03" "3.3.2" "OpenSSL"
.\" For nroff, turn off justification.  Always turn off hyphenation; it makes
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.nh
.SH "NAME"
OPENSSL_ia32cap \- the x86[_64] processor capabilities vector
.SH "SYNOPSIS"
.IX Header "SYNOPSIS"
.Vb 1
\& env OPENSSL_ia32cap=... <application>
.Ve
.SH "DESCRIPTION"
.IX Header "DESCRIPTION"
OpenSSL supports a range of x86[_64] instruction set extensions. These
extensions are denoted by individual bits in capability vector returned
by processor in \s-1EDX:ECX\s0 register pair after executing \s-1CPUID\s0 instruction
with EAX=1 input value (see Intel Application Note #241618). This vector
is copied to memory upon toolkit initialization and used to choose
between different code paths to provide optimal performance across wide
range of processors. For the moment of this writing following bits are
significant:
.IP "bit #4 denoting presence of Time-Stamp Counter." 4
.IX Item "bit #4 denoting presence of Time-Stamp Counter."
.PD 0
.IP "bit #19 denoting availability of \s-1CLFLUSH\s0 instruction;" 4
.IX Item "bit #19 denoting availability of CLFLUSH instruction;"
.IP "bit #20, reserved by Intel, is used to choose among \s-1RC4\s0 code paths;" 4
.IX Item "bit #20, reserved by Intel, is used to choose among RC4 code paths;"
.IP "bit #23 denoting \s-1MMX\s0 support;" 4
.IX Item "bit #23 denoting MMX support;"
.IP "bit #24, \s-1FXSR\s0 bit, denoting availability of \s-1XMM\s0 registers;" 4
.IX Item "bit #24, FXSR bit, denoting availability of XMM registers;"
.IP "bit #25 denoting \s-1SSE\s0 support;" 4
.IX Item "bit #25 denoting SSE support;"
.IP "bit #26 denoting \s-1SSE2\s0 support;" 4
.IX Item "bit #26 denoting SSE2 support;"
.IP "bit #28 denoting Hyperthreading, which is used to distinguish cores with shared cache;" 4
.IX Item "bit #28 denoting Hyperthreading, which is used to distinguish cores with shared cache;"
.IP "bit #30, reserved by Intel, denotes specifically Intel CPUs;" 4
.IX Item "bit #30, reserved by Intel, denotes specifically Intel CPUs;"
.IP "bit #33 denoting availability of \s-1PCLMULQDQ\s0 instruction;" 4
.IX Item "bit #33 denoting availability of PCLMULQDQ instruction;"
.IP "bit #41 denoting \s-1SSSE3,\s0 Supplemental \s-1SSE3,\s0 support;" 4
.IX Item "bit #41 denoting SSSE3, Supplemental SSE3, support;"
.IP "bit #43 denoting \s-1AMD XOP\s0 support (forced to zero on non-AMD CPUs);" 4
.IX Item "bit #43 denoting AMD XOP support (forced to zero on non-AMD CPUs);"
.IP "bit #54 denoting availability of \s-1MOVBE\s0 instruction;" 4
.IX Item "bit #54 denoting availability of MOVBE instruction;"
.IP "bit #57 denoting AES-NI instruction set extension;" 4
.IX Item "bit #57 denoting AES-NI instruction set extension;"
.IP "bit #58, \s-1XSAVE\s0 bit, lack of which in combination with \s-1MOVBE\s0 is used to identify Atom Silvermont core;" 4
.IX Item "bit #58, XSAVE bit, lack of which in combination with MOVBE is used to identify Atom Silvermont core;"
.IP "bit #59, \s-1OSXSAVE\s0 bit, denoting availability of \s-1YMM\s0 registers;" 4
.IX Item "bit #59, OSXSAVE bit, denoting availability of YMM registers;"
.IP "bit #60 denoting \s-1AVX\s0 extension;" 4
.IX Item "bit #60 denoting AVX extension;"
.IP "bit #62 denoting availability of \s-1RDRAND\s0 instruction;" 4
.IX Item "bit #62 denoting availability of RDRAND instruction;"
.PD
.PP
For example, in 32\-bit application context clearing bit #26 at run-time
disables high-performance \s-1SSE2\s0 code present in the crypto library, while
clearing bit #24 disables \s-1SSE2\s0 code operating on 128\-bit \s-1XMM\s0 register
bank. You might have to do the latter if target OpenSSL application is
executed on \s-1SSE2\s0 capable \s-1CPU,\s0 but under control of \s-1OS\s0 that does not
enable \s-1XMM\s0 registers. Historically address of the capability vector copy
was exposed to application through \fBOPENSSL_ia32cap_loc()\fR, but not
anymore. Now the only way to affect the capability detection is to set
\&\fBOPENSSL_ia32cap\fR environment variable prior target application start. To
give a specific example, on Intel P4 processor
\&\f(CW\*(C`env OPENSSL_ia32cap=0x16980010 apps/openssl\*(C'\fR, or better yet
\&\f(CW\*(C`env OPENSSL_ia32cap=~0x1000000 apps/openssl\*(C'\fR would achieve the desired
effect. Alternatively you can reconfigure the toolkit with no\-sse2
option and recompile.
.PP
Less intuitive is clearing bit #28, or ~0x10000000 in the \*(L"environment
variable\*(R" terms. The truth is that it's not copied from \s-1CPUID\s0 output
verbatim, but is adjusted to reflect whether or not the data cache is
actually shared between logical cores. This in turn affects the decision
on whether or not expensive countermeasures against cache-timing attacks
are applied, most notably in \s-1AES\s0 assembler module.
.PP
The capability vector is further extended with \s-1EBX\s0 value returned by
\&\s-1CPUID\s0 with EAX=7 and ECX=0 as input. Following bits are significant:
.IP "bit #64+3 denoting availability of \s-1BMI1\s0 instructions, e.g. \s-1ANDN\s0;" 4
.IX Item "bit #64+3 denoting availability of BMI1 instructions, e.g. ANDN;"
.PD 0
.IP "bit #64+5 denoting availability of \s-1AVX2\s0 instructions;" 4
.IX Item "bit #64+5 denoting availability of AVX2 instructions;"
.IP "bit #64+8 denoting availability of \s-1BMI2\s0 instructions, e.g. \s-1MULX\s0 and \s-1RORX\s0;" 4
.IX Item "bit #64+8 denoting availability of BMI2 instructions, e.g. MULX and RORX;"
.IP "bit #64+16 denoting availability of \s-1AVX512F\s0 extension;" 4
.IX Item "bit #64+16 denoting availability of AVX512F extension;"
.IP "bit #64+17 denoting availability of \s-1AVX512DQ\s0 extension;" 4
.IX Item "bit #64+17 denoting availability of AVX512DQ extension;"
.IP "bit #64+18 denoting availability of \s-1RDSEED\s0 instruction;" 4
.IX Item "bit #64+18 denoting availability of RDSEED instruction;"
.IP "bit #64+19 denoting availability of \s-1ADCX\s0 and \s-1ADOX\s0 instructions;" 4
.IX Item "bit #64+19 denoting availability of ADCX and ADOX instructions;"
.IP "bit #64+21 denoting availability of VPMADD52[\s-1LH\s0]UQ instructions, aka \s-1AVX512IFMA\s0 extension;" 4
.IX Item "bit #64+21 denoting availability of VPMADD52[LH]UQ instructions, aka AVX512IFMA extension;"
.IP "bit #64+29 denoting availability of \s-1SHA\s0 extension;" 4
.IX Item "bit #64+29 denoting availability of SHA extension;"
.IP "bit #64+30 denoting availability of \s-1AVX512BW\s0 extension;" 4
.IX Item "bit #64+30 denoting availability of AVX512BW extension;"
.IP "bit #64+31 denoting availability of \s-1AVX512VL\s0 extension;" 4
.IX Item "bit #64+31 denoting availability of AVX512VL extension;"
.IP "bit #64+41 denoting availability of \s-1VAES\s0 extension;" 4
.IX Item "bit #64+41 denoting availability of VAES extension;"
.IP "bit #64+42 denoting availability of \s-1VPCLMULQDQ\s0 extension;" 4
.IX Item "bit #64+42 denoting availability of VPCLMULQDQ extension;"
.PD
.PP
To control this extended capability word use \f(CW\*(C`:\*(C'\fR as delimiter when
setting up \fBOPENSSL_ia32cap\fR environment variable. For example assigning
\&\f(CW\*(C`:~0x20\*(C'\fR would disable \s-1AVX2\s0 code paths, and \f(CW\*(C`:0\*(C'\fR \- all post-AVX
extensions.
.SH "RETURN VALUES"
.IX Header "RETURN VALUES"
Not available.
.SH "COPYRIGHT"
.IX Header "COPYRIGHT"
Copyright 2004\-2021 The OpenSSL Project Authors. All Rights Reserved.
.PP
Licensed under the Apache License 2.0 (the \*(L"License\*(R").  You may not use
this file except in compliance with the License.  You can obtain a copy
in the file \s-1LICENSE\s0 in the source distribution or at
<https://www.openssl.org/source/license.html>.